| PART |
Description |
Maker |
| BBS-15 BBS-1/4 BBS-2/10 BBS-1-8/10 BBS-10 BBS-1-6/ |
72-Mbit QDR™-II SRAM 2-Word Burst Architecture
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL™ Architecture
72-Mbit DDR-II SRAM 2-Word Burst Architecture
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL™ Architecture
36-Mbit QDR™-II SRAM 4-Word Burst Architecture
Fuse
256K (32K x 8) Static RAM
64/256/512/1K/2K/4K x 18 Synchronous FIFOs
Low-Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs
Neuron® Chip Network Processor
64-Kbit (8K x 8) Static RAM
72-Mbit QDR™-II SRAM 2-Word Burst Architecture 保险
|
NXP Semiconductors N.V.
|
| M5LV-320_192-10AI M5LV-512_104-6AC M5-192_74-15YC |
IND SHLD 3.3UH 9A RMS SMT
Fifth Generation MACH Architecture EE PLD, 7.5 ns, PQFP160
Fifth Generation MACH Architecture EE PLD, 12 ns, PBGA256
Fifth Generation MACH Architecture EE PLD, 12 ns, PQFP208
Fifth Generation MACH Architecture EE PLD, 20 ns, PQFP240
Fifth Generation MACH Architecture EE PLD, 12 ns, PQFP144
Fifth Generation MACH Architecture EE PLD, 15 ns, PQFP208
10-Bit Broadband Modem Mixed Signal Front End (MxFE®); Package: LFCSP (9x9mm, 7.10 exposed pad); No of Pins: 64; Temperature Range: Industrial EE PLD, 12 ns, PQFP144
12-Bit Broadband Modem Mixed Signal Front End (MxFE®); Package: LFCSP (9x9mm, 7.10 exposed pad); No of Pins: 64; Temperature Range: Commercial EE PLD, 15 ns, PQFP144
12-Bit Broadband Modem Mixed Signal Front End (MxFE®); Package: LFCSP (9x9mm, 7.10 exposed pad); No of Pins: 64; Temperature Range: Industrial EE PLD, 15 ns, PQFP144
Fifth Generation MACH Architecture EE PLD, 6.5 ns, PQFP240
CONNECTOR ACCESSORY EE PLD, 10 ns, PQFP100
Fifth Generation MACH Architecture EE PLD, 7.5 ns, PBGA352
Fifth Generation MACH Architecture EE PLD, 15 ns, PQFP100
Fifth Generation MACH Architecture EE PLD, 20 ns, PBGA352
Fifth Generation MACH Architecture EE PLD, 10 ns, PQFP160
Fifth Generation MACH Architecture EE PLD, 10 ns, PBGA352
Fifth Generation MACH Architecture EE PLD, 15 ns, PQFP160
Fifth Generation MACH Architecture EE PLD, 12 ns, PQFP160
Fifth Generation MACH Architecture EE PLD, 12 ns, PQFP240
Fifth Generation MACH Architecture EE PLD, 10 ns, PBGA256
Fifth Generation MACH Architecture EE PLD, 15 ns, PQFP240
Fifth Generation MACH Architecture EE PLD, 6.5 ns, PQFP208
Fifth Generation MACH Architecture EE PLD, 20 ns, PQFP208
Fifth Generation MACH Architecture EE PLD, 10 ns, PQFP208
CONNECTOR ACCESSORY EE PLD, 12 ns, PQFP100
Fifth Generation MACH Architecture EE PLD, 5.5 ns, PQFP100
Fifth Generation MACH Architecture EE PLD, 10 ns, PQFP240
Fifth Generation MACH Architecture
|
Lattice Semiconductor, Corp.
Lattice Semiconductor Corporation
|
| PRESENTATION |
Presentation - AMDNext Generation Microprocessor Architecture
AMDs Next Generation Microprocessor Architecture
|
Advanced Micro Devices
|
| CY7C1371D-100AXI CY7C1371D-100BGI CY7C1373D-100BZI |
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture 1M X 18 ZBT SRAM, 8.5 ns, PQFP100
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture 18兆位（为512k × 36/1M × 18）流体系结构，通过与NoBLTM的SRAM
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture 1M X 18 ZBT SRAM, 8.5 ns, PBGA165
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture 1M X 18 ZBT SRAM, 6.5 ns, PBGA119
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture 512K X 36 ZBT SRAM, 8.5 ns, PBGA165
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture 1M X 18 ZBT SRAM, 6.5 ns, PQFP100
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture 1M X 18 ZBT SRAM, 6.5 ns, PBGA165
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture 512K X 36 ZBT SRAM, 8.5 ns, PBGA119
|
Cypress Semiconductor Corp.
Cypress Semiconductor, Corp.
|
| CY7C1333 7C1333 CY7C1333-66AC CY7C1333-50AC |
64Kx32 Flow-Thru SRAM with NoBL Architecture(B>NoBL结构4Kx32流通式 SRAM)
64Kx32 Flow-Thru SRAM with NoBL⑩ Architecture
From old datasheet system
|
Cypress Semiconductor Corp.
|
| CY7C1550KV18-450BZC CY7C1550KV18-400BZC CY7C1548KV |
Sync SRAM; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 2M X 36 DDR SRAM, 0.45 ns, PBGA165
72-Mbit DDR II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
|
Cypress Semiconductor, Corp.
|
| CY7C1355B-117BGI CY7C1355B-117BZC CY7C1355B-117BGC |
9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture 9 - MB的（256 × 36/512K × 18）流体系结构，通过与总线延迟静态存储器
9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture 256K X 36 ZBT SRAM, 7.5 ns, PBGA165
9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture 256K X 36 ZBT SRAM, 6.5 ns, PBGA165
9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture 256K X 36 ZBT SRAM, 7 ns, PQFP100
|
Cypress Semiconductor Corp.
Cypress Semiconductor, Corp.
|
| CY7C1315AV18-250BZC CY7C1311AV18 CY7C1311AV18-167B |
18-Mb QDR(TM)-II SRAM 4-Word Burst Architecture
18-Mb QDRTM-II SRAM 4-Word Burst Architecture
|
CYPRESS[Cypress Semiconductor]
|
| CY7C1460AV33-167AXC CY7C1460AV33 CY7C1460AV33-167A |
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL垄芒 Architecture
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL Architecture
|
Cypress Semiconductor
|
| CY7C1352G06 CY7C1352G-250AXC CY7C1352G-250AXI CY7C |
4-Mbit (256K x 18) Pipelined SRAM with NoBL⑩ Architecture
4-Mbit (256K x 18) Pipelined SRAM with NoBL Architecture
|
Cypress Semiconductor
|
| CY7C1314BV18 CY7C1312BV18 |
18-Mbit QDR庐 II SRAM Two-Word Burst Architecture
18-Mbit QDR? II SRAM Two-Word Burst Architecture
|
Cypress Semiconductor
|
| CY7C1410JV18-267BZC CY7C1410JV18-267BZI CY7C1410JV |
36-Mbit QDR垄芒-II SRAM 2-Word Burst Architecture
36-Mbit QDR?II SRAM 2-Word Burst Architecture
|
Cypress Semiconductor
|
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